Prior art programmable logic devices can perform diverse logic functions. These functions include computing combinatorial logic functions such as AND, NAND, XOR, as well as storing such logic functions. Further, particular inputs can be selected from multiple inputs to a chip. U.S. Pat. No. 4,870,302 describes an invention of Xilinx, Inc., assignee of the present invention, for performing such functions. U.S. Pat. No. 4,706,216 describes a logic element used by Xilinx, Inc. to generate logic functions. These two patents are incorporated herein by reference. Products made as described in the above two patents are general and powerful, able to perform selectable logic functions of many variables and able to be reprogrammed by a user to change which logic functions are generated. Devices made by Xilinx, Inc. are described in "The Programmable Gate Array Data Book," available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, incorporated herein by reference.
In order to direct the signals around a logic array chip to a particular logic element which will perform the desired function, it may be desired to buffer a signal before placing it onto an interconnect line. This is particularly true of signals coming from off the chip or going off the chip. U.S. Pat. No. 4,855,619 discloses a structure for controlling placement of signals from a plurality of lines onto another line, with buffering if the line is of sufficiently high capacitance to need buffering. Signals placed onto this interconnect line may be generated by a logic element of the type described in U.S. Pat. No. 4,706,216.
Some simple logic functions do not require the general and powerful abilities of the configurable logic element described in U.S. Pat. No. 4,706,216. Further, such simple logic functions might be used together with other more complex functions for which the full abilities of a configurable logic array chip are needed. One such simple function is the AND function. To perform this function quickly, manufacturers provide a wide wired AND gate such as shown in FIG. 1. Suppose that each of the transistors is N-channel and that the inputs I.sub.1 -I.sub.3 to the function are applied through inverters INV.sub.1 -INV.sub.3 to the gates of transistors N.sub.1 -N.sub.3 respectively. When any of transistors N.sub.1 -N.sub.3 is turned on by a low input signal on I.sub.1, I.sub.2, or I.sub.3, interconnect line IC will be pulled to ground, generating a logical 0 output signal. Only when all inputs I.sub.1 -I.sub.3 are high will all transistors N.sub.1 through N.sub.3 be off so that resistor R.sub.1 can pull the interconnect line IC high to produce a logical 1 output signal. Thus the signal on interconnect line IC is the AND-function of the signals I.sub.1 -I.sub.3.
Xilinx, Inc. provides a means of performing such a function in a configurable logic array chip. A buffer usable for such a purpose may be as shown in FIG. 2 and described in U.S. Pat. No. 4,855,619, which is incorporated herein by reference. The circuit of FIG. 2 can be programmed to present a high impedance to line LL1 when the value on line L1 is high and a low voltage when the value on line L1 is low. A high value in memory cell M61 turns on N-channel transistor T61, placing the signal from line L1 onto line L2. A low value in memory cell M41 turns on transistor T42 and turns off transistor T41 placing the signal from line L1 into inverter B41 which puts the complement of the signal on line L1 onto the gate of transistor T32. Thus a high value of L1 turns off transistor T32, presenting a high impedance on line LL1 whereas a low signal on L1 turns on transistor T32 and is propagated through T32 to line LL1. A plurality of lines such as L1 and L3 can be connected this way to line LL1, which in combination with resistor R62 can generate the AND function.
While this more sophisticated wired-AND gate has many advantages, there are still some occasions where further flexibility is desirable. For example, in complex information processing applications it is sometimes desired to have more than one logical function of the same set of variables available simultaneously. Additionally, if the logic function of the complement of an input signal is required, that input signal will first have to be routed to a logic element where it will be inverted. Then the inverted signal will have to be routed back to line LL1 which will generate the AND function of the inverted input signal and other signals. Generating the complement of an input signal in this way has two disadvantages. Firstly, it slows down the speed of information processing. Secondly, it uses valuable resources in the interior of the chip which could otherwise be available for performing more complex functions.